P6470 TTL/CMOS Probe
Number of Data Outputs –
16 in Full Channel Mode.
8 in Half Channel Mode.
Number of Clock Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Number of Strobe Outputs – 1. (Only one of Clock
Output and Strobe Output can be enabled.)
Clock Output Polarity – Positive.
Strobe Type – RZ only.
Strobe Delay – Zero or Trailing Edge.
Output Type –
HD74LVC541A for Data Output.
HD74LVC244A for Clock/Strobe Output.
Rise/Fall Time (20% to 80%) – Timing values
measured using 75 Ω termination (internal to
probe), 1 MΩ + <1 pF load and VOH set to 5.0 V
Clock/Strobe Output –
Rise: 640 ps typical.
Fall: 1.1 ns typical.
Data Output –
Rise: 680 ps typical.
Fall: 2.9 ns typical.
Rise/Fall Time (20% to 80%) – Timing values
measured using 75 Ω termination (internal to
probe), 510 Ω + 51 pF load and VOH set to 5.0 V.
Clock/Strobe Output –
Rise: 6.5 ns typical.
Fall: 6.3 ns typical.
Data Output –
Rise: 5.2 ns typical.
Fall: 4.5 ns typical.
Series Terminator Resistor – 75 Ω standard; 43,
100 and 150 Ω optional.
Output Voltage (nominal, load: 1 MΩ) – VOH.
2.0 V to 5.5 V, tri-statable, programmable in
25 mV increments.
Data Output Skew –
<570 ps typical between all data output pins of all
modules in the mainframe after inter-module skew
is adjusted manually.
<440 ps typical between all data output pins of
single probe.
Data Output to Strobe Output Delay – 1.7 ns
typical when strobe delay set to zero.
Data Output to Clock Output Delay – 2.4 ns typical.
External Clock Input to Clock Output Delay –
Full channel mode: 61 ns typical.
Half channel mode: 61 ns typical.
Number of External Event Inputs – 1.
Number of External Inhibit Inputs – 1.